Re: mlnx_tune does not detect the BIOS I/O non-posted prefetch settings?

IMHO this mlnx_tune Python script has a bug.  The logic used in issuing the warning message is incorrect.

  1462                  pci_width_compatible_to_cpu_ok = not (int(self.actual_pci_width) >= PciDeviceInfo.MIN_LENGTH_CHECK_HSW_COMPATIBLE and cpu_arch == Architecture.HASWELL)

In the same code,

  1408          MIN_LENGTH_CHECK_HSW_COMPATIBLE         = 16

Now if you follow the logic, the result is:

int(self.actual_pci_width) >= PciDeviceInfo.MIN_LENGTH_CHECK_HSW_COMPATIBLE is 16 >= 16 is True

Architecture.HASWELL is also True

True and True is True

not True is False

pci_width_compatible_to_cpu_ok is false

But this is invalid! EDR needs PCIe gen3 x 16. That's mandatory, so why the script complains?  Using lspci -vv, it's easy to see the following:

LnkCap: Port #0, Speed 8GT/s, Width x16, ASPM not supported, Exit Latency L0s unlimited, L1 unlimited
                       ClockPM- Surprise- LLActRep- BwNot-

See the above Width x16 ?

So, if the lspci correctly reports an EDR HCA in the system and it's in a PCIe Gen3 x 16 slot, the mlnx_tune issues a warning?   This is a bug I am afraid.